1. Field of Invention
This invention relates generally to the field of testing of integrated circuits and systems, and particularly to boundary scan testing via a machine with an interactive user interface providing real-time monitoring and control of boundary scan enabled devices and systems without requiring the use of test vectors, test executives, netlists, or schematics.
2. Prior Art
Each year electronic circuits and systems get smaller. As a result, the ability to test the smaller circuits with traditional test equipment is becoming more and more of a challenge. In the early 1980's, this issue was recognized and in 1985 a group of electronics and semiconductor manufacturers formed the Joint Test and Access Group (JTAG) to develop a standard for building testability features into the semiconductor devices. The standard was adopted in February 1990 as “IEEE 1149.1-1990, IEEE Standard Test Access Port and Boundary Scan Architecture.” This standard is focused on providing test methodology to identify manufacturing defects such as soldering errors, missing components, broken wire bonds, and bad part orientation.
IEEE 1149.1 is now commonly used by the manufacturing community to test for defects and several tools are available that provide excellent test coverage of electronic assemblies. Unfortunately, even though the standard has been in place for over 10 years, design engineers and the electronics design community in general have not adopted boundary scan testing. This is due to a lack of tools that are inexpensive and easy to learn and use with little or no prior understanding of boundary scan. Without readily available easy-to-use boundary scan tools, engineers have to resort to crude trial-and-error test methodology which is expensive and time-consuming.
Boundary scan tools available today typically cost anywhere from $10,000 for bare-bones tools to more than $50,000 for full-featured tools. These costs are prohibitive for an average design engineer that simply wants to know if a part is soldered to a board correctly.
Further, while the tools that are available today are very powerful, unfortunately they are also very complicated and difficult to learn and use. First a schematic netlist must be run through an Automatic Test Pattern Generator (ATPG) to generate test vectors and a test executive must be created to setup the Boundary Scan operations. The test executive then runs the test patterns through all of the devices and produces a static report that identifies potential errors. These tools have a steep learning curve and require a fundamental understanding of boundary scan that most design engineers do not have today. Additionally, in order to cover as much of the circuitry on a board as possible, including components that are not boundary scan enabled, test points and probes must be added to the circuitry to provide the scan tools access to those otherwise inaccessible components. This creates additional cost and complications.
Traditional boundary scan tools produce a static output report that does not lend itself to simple interactive debugging of the integrated circuits under test.